In conventional communication systems, a microprocessor is usually applied for dealing with software program control and part of the DSP algorithm with less computation requirement, and an associated hardware accelerator is responsible for the complex DSP algorithm. The implementation for the hardware accelerator is usually accomplished with an application-specific integrated circuit (ASIC). While, because of the rapid development of wireless communication technology and the becoming shorter and shorter cyclic lifetime of the relative products in market, there is an appeal already urging for an advanced reconfigurable and programmable hardware accelerator.
However, such a solution doesn't really relieve the high CPU dependence on a portable multi-function device. The CPU time is usually used to execute a single task. And it's absolutely impractical and uneconomical for a system designer to change the CPU with the price or performance consideration.
FIG. 1 is a block diagram illustrating a conventional reconfigurable radio communication device. As shown in FIG. 1, the conventional reconfigurable radio communication device is mainly comprised of a programmable processor 101, a heterogeneous reconfigurable multi-processor 103, and a system bus 107 connecting the processor 101 with the multi-processor 103. In the radio communication device, the reconfigurable multi-processor 103, which is composed of a plurality of co-processors to serve for an accelerator in the system, is generally accomplished with ASICs and programmable logic devices. A framework like this is defective in that the routing area of the programmable logic device is extraordinary large and the power consumed is considerable. Another disadvantage of this communication framework is that the CPU needs to arrange all the tasks in the system between the components in the communication device.
Another communication framework of reconfigurable multi-processor was disclosed in U.S. Pat. No. 5,790,817. As shown in FIG. 2, this communication framework uses a micro-scheduler 201 to arrange the working schedule between digital signal processors (DSPs) 203 and 205 to thereby decrease the dependence degree upon CPU. However, using the DSP to deal with the digital signal processing for the bit stream data is not an optimized solution.
To improve both efficiency and power consumption on portable multi-function devices, this invention is intended to provide a new communication framework for a radio processor. In a platform, a user may entail most part of communication tasks to be processed on the radio processor so that the dependence degree on CPU could be decreased. Besides, the radio processor has optimized the conditions of the communication system and relative hardware based on the premise capable of realizing different standards.